Technical Lead

Job Description :

We are looking for an experienced ASIC RTL Design Engineer to join our team and contribute to the design, development, and implementation of next-generation SoC/IP solutions.

Key Responsibilities

• RTL design & micro-architecture development (Verilog/SystemVerilog)
• End-to-end ASIC front-end flow: spec RTL synthesis STA support
• Block/IP integration, lint/CDC, timing & power optimization
• Debugging, simulation, and cross-functional collaboration with DV/PD/DFT teams

Requirements

• Strong digital design fundamentals
• Hands-on experience with ASIC flows & EDA tools (DC, VCS/Xcelium, SpyGlass)
• Knowledge of bus protocols (AXI/AHB/PCIe/DDR)
• Scripting (Python/TCL) is a plus

Qualifications:

• B.E./B.Tech. degree at minimum.