Synthesis Lead

Job Description:

• Experience: 6 to 10 years
• Leading synthesis, logical equivalence, constraint development, and STA activities
• Strong knowledge of both logical and physical synthesis flows
• Hands-on experience with LEC using Conformal Low Power.
• Drive front-end low-power implementation and optimization using UPF.
• Familiar with multi-mode, multi-corner (MCMM) timing closure, signal integrity, and noise analysis flows.
• Familiar with Subsystem level & Chip level Timing closure.
• Experienced in manual timing fixes and ECO generation across MCMM corners.
• Collaborate closely with RTL, DFT, and physical design teams to optimize front-end (RTL-to-netlist) implementation for performance, power, and area (PPA).
• Strong understanding of SDC constraints with the ability to translate timing requirements into accurate constraint definitions.
• Good understanding in scan architecture and various DFT modes & PnR methodologies are preferred.
• Actively mentor new team members to build and strengthen technical skills.
• Work closely with the project lead to define schedules, track progress, and proactively raise issues and risks to project management.
• Exposure to Cadence tools like Genus, Tempus, Conformal would be preferred

Interested can share your resume at:

vaishnavi.suvarna@acldigital.com