Senior RTL Design Engineer

Job Title: Senior FPGA RTL Design Engineer / Principal FPGA Engineer

Experience: 10 Years Above

Location: Bangalore (Onsite)

Employment Type: Full-Time

Role Overview

We are seeking a highly skilled and experienced FPGA RTL Design Engineer with deep handson expertise in RTL coding, FPGA build flows, integration, prototyping, and custom IP development. The ideal candidate will bring strong experience in FPGA platforms, highspeed interfaces, ASICtoFPGA conversion, and systemlevel debugging, along with proven contributions across multiple semiconductor organizations.

This role requires strong ownership, technical depth, and the ability to collaborate across digital, verification, ASIC, and crossfunctional engineering teams.

Key Responsibilities

FPGA RTL Design & Integration

• Develop and integrate RTL modules using Verilog/SystemVerilog for complex FPGAbased systems.
• Convert ASIC designs to FPGA implementations, ensuring functional equivalence and performance optimization.
• Perform FPGA build flows, manual partitioning, synthesis, timing closure, and onboard bringup.

FPGA Prototyping & System Development

• Lead FPGA prototyping activities for largescale designs (Flash controllers, Protocol Stack, Custom IPs).
• Work with highend FPGA families (Xilinx Spartan/Artix/Kintex/Zynq/Virtex Ultrascale+ and Intel/Altera MAX10).
• Develop microarchitecture specifications, technical documentation, and design collateral.

Debugging, Validation & Support

• Perform debug analysis, rootcause investigation, and issue resolution on FPGA hardware.
• Support crossfunctional teams (ASIC, firmware, system validation) with FPGAbased test setups.
• Conduct silicon validationstyle testing for prototype systems.

Custom IP Design & Hardware Projects

• Design custom IP including oscillator interfaces, AXI/APB/SPI/I2C-based blocks, and highspeed communication modules.
• Develop FPGA board bringup solutions, hardware debugging, and manufacturing readiness documentation.

Tools, Automation & Scripting

• Work with FPGA toolchains including Xilinx Vivado/ISE, Altera Quartus, HAPS Protocompiler, Xcelium.
• Use Tcl, Shell, Python scripts for automation, build flow enhancements, and testing.

Required Skills & Qualifications

• 10+ years of experience in FPGA RTL design, integration, and prototyping.
• Strong expertise in Verilog/SystemVerilog, RTL architecture, and custom IP development.
• Experience with FPGA families across Xilinx, Intel/Altera, and associated toolchains.
• Working knowledge of protocols: SPI, AXI4, APB, I2C, Avalon, PCIe basics, AHB, DCI, SSB.
• Handson experience in FPGA build flow, timing analysis, debugging, and system testing.
• Familiarity with Linux environments, GitHub/Bitbucket, and scripting (Tcl, Shell, Python).
• Experience with MODEM protocol stack, QA testing, and throughput validation in telecom projects.
• Bachelors degree in ECE/Electronics Engineering (preferred: strong academic background).

Preferred / Nice-to-Have

• Experience with ASIC/FPGA codevelopment and design verification concepts.
• Understanding of CDC, timing constraints, synthesis methodologies.
• Exposure to custom FPGA board design, reviews, and hardware debugging.
• Knowledge of DC synthesis, Lint tools, and mixedsignal interfaces.

Why Join Us

• Opportunity to work on advanced FPGA systems, largescale architectures, and nextgeneration storage & communication solutions.
• Ownership of critical FPGA subsystems including build flow, IP design, and architecture.
• Work with cuttingedge tools, complex designs, and highperformance engineering teams.
• Strong career growth in FPGA, SOC, and systemlevel architecture domains.