Senior Manager - ASIC Development Engineering (DFT)

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Today’s exceptional challenges require your unique skills. It’s You & Sandisk. Together, we’re the next BIG thing in data.

We are seeking a highly skilled and experienced DFT Engineer to join our dynamic team of engineers to develop the next-generation Flash Controllers. As an SoC DFT Engineer, you will be responsible for defining and implementing industry leading DFT solutions, with emphasis on SCAN, MBIST, BSDL etc. The ideal candidate will have a deep understanding of DFT Architecture, Implementation flow, MBIST, SCAN ATPG & Simulation expertise.

ESSENTIAL DUTIES AND RESPONSIBILITIES:

• DFT Architecture definitions for SoC development
• Leading complex activities and providing solutions for complex DFT problems.
• Collaborate with cross-functional teams to define and refine SoC DFT requirements, ensuring alignment with industry standards and customer needs.
• Working closely with the Design, Verification, Physical Design & Test Engineering teams while guiding them on the test requirements and methodologies.
• Work closely with the Product Engineering team and understand the test requirements, get involved in complex silicon debugs.
• Evaluate all aspects of the SoC DFT flow from requirements, through detailed definitions, and work closely with the CAD to continuously improve the DFT methodology.

• B.Tech / M,Tech / Phd  in Electronics,  Computer science or Electrical Engineering
• Minimum 16+ years of experience in DFT
• Strong understanding of DFT Architecture

SKILLS:

• Extensive experience in SoC DFT architecture, DFT IP development and DFT methodology.
• Proven track record of driving DFT architecture in complex ASIC designs.
• Work independently on multiple complex DFT problems across different projects.
• Proficiency in ASIC DFT Implementation tools, simulation methodologies, and hardware description languages (HDLs).
• Proficiency in SCAN, MBIST implementation.
• Solid understanding of JTAG & BSDL standards.
• Good understanding on Test clocking requirements, Test mode timing closure.
• Proficiency in complex silicon debugs and yield analysis.
• Solid understanding of SoC architecture and low-power design principles.
• Understanding of High-Speed interfaces (PCIe or UFS protocols) and experience with SSD/Flash is advantage.
• Excellent analytical and problem-solving skills.
• Strong communication skills and the ability to work effectively in cross-functional teams.

Sandisk is committed to providing equal opportunities to all applicants and employees and will not discriminate based on their race, color, ancestry, religion (including religious dress and grooming standards), sex (including pregnancy, childbirth or related medical conditions, breastfeeding or related medical conditions), gender (including a person’s gender identity, gender expression, and gender-related appearance and behavior, whether or not stereotypically associated with the person’s assigned sex at birth), age, national origin, sexual orientation, medical condition, marital status (including domestic partnership status), physical disability, mental disability, medical condition, genetic information, protected medical and family care leave, Civil Air Patrol status, military and veteran status, or other legally protected characteristics. We also prohibit harassment of any individual on any of the characteristics listed above. Our non-discrimination policy applies to all aspects of employment. We comply with the laws and regulations set forth in the Equal Employment Opportunity is the Law poster.

Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution.

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