Position:

Job Description:

Job Description:

• Strong knowledge of UVM, advance UVM, System Verilog. (Universal Verification Methodology)
• Must have worked on development of test-plan, testbench components, verification environment, interface agents, Scoreboard in UVM.
• Understanding of complete functional verification cycle will be added advantage.
• Knowledge of at least one industry standard protocols like Ethernet, PCIe, MIPI, USB, AMBA or similar is required.
• Skills to debug RTL & testbench issues, test failures.
• Experience on verification closure by closing Coverage and bug reports.
• Primarily knowledge of Script development and maintenance
• Understanding of customer dynamic environment change and adopt run time changes in schedule, design etc

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