Senior Design Verification Engineer

Digital Verification Engineer

Experience: 7 + Experience

Preferred Location: Bangalore / Ahmedabad

Role Overview

We are seeking an experienced Digital Verification Engineer who can work independently and drive

verification activities across multiple digital functional domains. The ideal candidate will have strong

expertise in UVM-based verification methodologies and hands-on execution skills, with the ability to

mentor junior engineers when required.

Key Responsibilities

Develop and update custom UVM verification environments including models, predictors,

and specialized components.

Maintain and enhance existing UVCs through bug fixes and extensions.

Create and update tests/sequences to improve coverage and verification efficiency.

Define functional coverage and ensure alignment with the verification plan.

Debug regressions, including gate-level simulations.

Provide support and guidance to junior engineers on verification methodology.

Create and debug digital models of analog blocks.

Collaborate with cross-functional teams to ensure verification completeness.

Desired Skills & Experience

7+years of hands-on digital verification experience.

Strong knowledge of UVM methodology and System Verilog.

Proven ability to work with minimal supervision and deliver results.

Experience in RFID chip verification or RF system verification is a strong advantage.

Excellent debugging and problem-solving skills.

Ability to mentor and guide junior engineers (while maintaining focus on execution).

Good To Have

• SOC-Level Verification Experience
• Coverage -Driven Verification Methodology
• Scripting Knowledge
• Experience Working in Fast-Paced, Customer-Facing projects

What We Offer

Opportunity to work on cutting-edge verification projects.

Collaborative environment with scope for both hands-on execution and technical

leadership.

Growth opportunities in advanced verification methodologies and RF-related domains