Principal/Senior Design Verification Engineer

TITLE: DESIGN VERIFICATION ENGINEER

LOCATION: GREATER BENGALURU AREA

Company Description

We are looking for exceptional talent and leadership to join Fast Growing Startup into Scalable Intelligence, the worlds first company developing Agentic Silicon for powering the future of AI.

Founded in 2023, We have deep customer engagements across America, Europe, and Asia, and demonstrated functional prototypes to prove our concept and vision.

Job Description

The verification Engineer position is your opportunity to join one of the industrys leading companies in Smart Edge SoCs for network/systems control, management security systems, and IIoT.

You will be responsible for RTL SoC/Subsystem verification of ARM-based SoCs, and work on industry-standard verification methodologies like UVM, Portable Stimulus, and Formal verification flows. You will report to the Director of Engineering (Verification).

KEY RESPONSIBILITIES

• Help develop test plan definition
• Micro-architecture design verification, RTL verification, and documentation
• Top-level and block-level functional and performance verification, and system-level use-case verification; and
• Support test program development, chip validation, and chip life until production maturity.
• Team Management and Building
• Collaboration with firmware, software, DV, FPGA, DFT, SoC integration, and backend teams throughout various stages of ASIC development.

Qualifications

• 8-15 years of experience in UVM verification and UVM environment development (must have)
• Proficient in test plan definition and test case development in C/Assembly/System Verilog
• Expertise in verifying design at RTL level and gate-level simulation
• Good understanding of coverage analysis, performance verification, and use-case verification.
• Must have worked on AMBA AXI, AHB, and APB protocols
• Should have worked on verifying interface protocols like PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART, etc.
• Experience in Jasper which is a formal verification platform from Cadence that helps with design verification at every stage of the design cycle
• Fluency with scripting languages (e.g., Perl, Python, Shell); and
• Experience in working with repository management tools like Bitbucket/ Jenkins and bug-tracking tools like JIRA.
• BE/BTECH or ME/MTECH degree in EE/EECS/CS or equivalent.

Contact

Sumit S. B

"Mining the Knowledge Community"

Practice Head(Talent Acquisition. Semiconductors Domain)