Principal Engineer

We are looking for an experienced Senior Architecture Leader to define and drive next-generation MCU chiplet architectures and Die-to-Die (D2D) interface IPs. This role offers a chance to work at the intersection of system architecture, microarchitecture, and cross-functional execution.

Key Responsibilities

• Define and drive chiplet architecture optimized for MCU constraints
• Lead architecture of D2D interface IPs (UCIe / Bunch-of-Wire)
• Collaborate closely with product and software architects
• Shape microarchitecture of IP blocks and subsystems
• Work with verification teams on test-plan development and reviews
• Collaborate with Design, Validation, DFT, Physical Design, and Emulation teams
• Support post-silicon debug and functional validation
• Drive IP selection and make/buy decisions

Qualifications & Experience

• BTech / MTech in EE / ECE / Computer Engineering / Computer Science
• 15+ years of hands-on hardware architecture experience
• Strong communication, problem-solving, and teamwork skills
• Experience with D2D protocols (UCIe, Bunch-of-Wire)
• Expertise in MCU/Microprocessor architecture, interconnects, cache coherency
• Experience benchmarking and tuning IP/SoC performance
• Strong knowledge of AHB/AXI/CHI, memory systems (ROM, RAM, Flash, LPDDR/DDR3/4)
• Deep understanding of clocking, power management, system modes, debug, security

Good to Have

• NIC / FlexNOC interconnect experience
• Flash memory subsystems
• Power management architecture
• Virtual Prototyping tools: ARM Fast Models, Synopsys Virtualizer, Wind River SIMICS

What Were Looking For

• A can-do attitude and openness to diverse teams and cultures
• Passion for building scalable, high-performance architectures