Analog Chip Lead - Power Management

About team

MPP organization develops high performance multiphase buck regulator solutions, controller as well as power FETs for Industrial, automotive and enterprise markets. Our products include multiphase converters supporting >800W of power delivery for high end servers with high phase/rail count. Key focus area for this group is to deliver industry leading power conversion solution with best in class efficiency, power density and transient performance which opens up a huge opportunity for innovation in design as well as methodologies.

Experience : 5-15 years of analog & mixed signal IC Design

Basic Job Qualifications

Strong competency in transistor level design and implementation of various Analog functions.

• Strong competency in small signal analysis and various frequency compensation techniques.
• Experience in designing precision analog circuits like operational amplifiers, Band-gap references, POR, Current Limit circuits, LDO regulators, comparators, oscillators etc.
• Good understanding of device behavior, limitation, safe operation area etc.
• Top-level integration, Block-level verification across PVT, Statistical Mismatch.
• Experience with Silicon validation and debug.
• Good communication, presentation skills and teamwork.

Preferred Qualification

• Experience in high power DC-DC regulators
• Proven track record of Innovation and Execution.
• Creative in topology selection that optimizes silicon area and power consumption.
• Experience with products with complex analog digital interfaces
• Understanding of chip level ESD/LU requirements.

Primary Responsibility

• Lead the full chip development starting from definition to RTM (Release to the Market).
• Work closely with marketing and systems teams to refine product specifications.
• Derive block level specification and select the topology based on product requirements.
• Generate top-level simulation plan and collaborate with verification engineer for best coverage.
• Work closely with Layout engineer to get optimized IC layout by minimizing parasitic elements.
• Validate Silicon, assist characterization and participate in De-bug process
• Mentor 1-2 people