Senior STA Engineer

ACL Digital is hiring!!

Job Title: Senior STA Engineer

Experience: 4 to 312Years

Location: [Insert Location Bangalore/Hyderabad

Company: ACL Digital

Job Type: Full-Time | Permanent

Domain: Semiconductor STA Engineer

Job Description:

We are looking for a skilled Static Timing Analysis (STA) Engineer to join our team. The ideal candidate will have strong expertise in timing analysis and closure for complex SoC designs, working closely with design and physical implementation teams.

Key Responsibilities:

• Perform Static Timing Analysis (STA) for block and full-chip level designs
• Drive timing closure across all PVT corners and modes
• Analyze and debug timing violations (setup, hold, transition, etc.)
• Work on constraints development and validation (SDC)
• Collaborate with synthesis, PnR, and design teams to resolve timing issues
• Support ECO implementation and timing sign-off
• Generate and review timing reports

Required Skills:

• Strong hands-on experience with STA tools like Synopsys PrimeTime
• Good understanding of timing concepts, clock domains, and constraints
• Experience with synthesis and place & route flows
• Familiarity with scripting languages (Tcl, Perl, or Python)
• Knowledge of low-power design and multi-voltage domains is a plus

Qualifications:

• Bachelors/Masters degree in Electronics / VLSI / Electrical Engineering
• 4+ years of relevant industry experience in STA

Preferred:

• Experience with advanced nodes (e.g., 7nm, 5nm)
• Exposure to sign-off flows and methodologies

If you want, I can also tailor this JD for LinkedIn posting, referral message, or make it more company-specific (ACL branding tone, perks, etc.).

Interested can share your resume at: Anusha Prakash

anusha.prakash@acldigital.com