Senior Physical Design Engineer

Physical Design Engineer

Location: Bengaluru(on-site)

Experience: 312 Years

Employment Type: Full-time

About the Role

We are looking for a highly motivated Physical Design Engineer to join our VLSI/ASIC implementation team. The candidate will be responsible for end-to-end physical design activities for advanced technology nodes, working closely with RTL, DFT, STA, and signoff teams to deliver high-performance and low-power semiconductor products.

Key Responsibilities

• Perform full-chip and block-level physical design implementation from netlist to GDSII
• Handle floorplanning, power planning, placement, CTS, routing, and physical verification
• Drive timing closure, congestion reduction, power optimization, and area optimization
• Work on advanced nodes such as 7nm/5nm/3nm technologies
• Analyze and fix setup/hold violations across multiple modes and corners
• Perform ECO implementation and timing signoff support
• Collaborate with frontend, DFT, STA, verification, and packaging teams
• Ensure clean DRC/LVS and support tapeout activities
• Develop and improve automation scripts for PD flow enhancement

Required Skills

• Strong understanding of ASIC Physical Design flow
• Hands-on experience with:
• Floorplanning
• Placement & Optimization
• Clock Tree Synthesis (CTS)
• Routing
• STA and timing closure
• IR drop and power analysis
• Physical verification (DRC/LVS)

Experience with industry-standard EDA tools such as:

• Cadence Innovus
• Synopsys ICC2
• PrimeTime
• Tempus
• Fusion Compiler

Qualifications

• Bachelors or Masters degree in Electronics / VLSI / Electrical Engineering
• Strong debugging and problem-solving skills
• Excellent communication and teamwork abilities