Senior DFT Engineer

JOB DESCRIPTION

Position: Sr DFT Engineer (Lead) ATPG & Scan Insertion

Experience: 1215 Years

Role Overview

We are looking for a Senior DFT Engineer with deep expertise in ATPG and Scan Insertion to support highcomplexity SoC programs for our semiconductor clients. This role requires strong technical ownership across the DFT lifecycle and the ability to deliver manufacturingready, highquality test solutions in a fastpaced, multistakeholder environment.

Key Responsibilities

• Lead DFT definition, implementation, and signoff for complex SoCs and IPs
• Own Scan Insertion and Scan Compression strategies aligned with performance, area, and test cost goals
• Develop, debug, and optimize ATPG patterns (stuckat, transition, atspeed) to achieve high fault coverage
• Partner with client engineering teams across RTL, Synthesis, Physical Design, and Validation
• Identify and resolve DFT/ATPG bottlenecks, including coverage gaps and pattern inefficiencies
• Support silicon bringup, tester correlation, and customer test readiness milestones
• Ensure adherence to client DFT standards, schedules, and quality expectations
• Provide technical guidance and mentoring to junior DFT engineers on the project

Required Expertise

• 1012 years of handson experience in DFT implementation and ATPG signoff
• Strong working knowledge of:
• Scan architectures and scan compression methodologies
• Fault models: stuckat, transition, path delay
• Atspeed and timingaware ATPG
• Practical experience using leading commercial DFT tools (Synopsys, Cadence, or Siemens platforms)
• Strong understanding of RTL design flow, synthesis constraints, and timing concepts
• Proven ability to work with large, multisite client teams and meet aggressive program milestones