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Opening for FPGA Development with PCie - Bangalore

UST

2 - 5 years

Bengaluru

Posted: 30/04/2026

Job Description

Hi


We do have an opening for FPGA design and Development 12+years.


  • Good Experience FPGA Development with PCie, Gen4/Gen5/Gen6
  • Knowledge in space standards (ECSS and CE)
  • Experience in digital ASICs design and synthesis
  • Experience in FPGA design methodologies including high speed design, serial protocols and FPGA timing closure is required


Please share your resume to jayalakshmi.r2@ust.com


Regards,

Jaya

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