Lead Full Chip STA

Bangalore, Hyderabad, Pune & Ahmedabad

About Company:

Role: Lead STA Engineer

About

We are a leading technology consulting and solutions development firm specializing in the VLSI, Cloud Computing, Cyber Security, and AI/ML domains. Our success is anchored in the unparalleled expertise of our engineering leadership team, whose collective experience spans renowned tech giants like Google, Cisco, Microsoft, Oracle, Uber, Broadcom, and Sun. With a commitment to innovation and excellence, we deliver cutting edge solutions that empower businesses to thrive in the ever-evolving digital landscape.

Experience: 8 to 14 years

Location: Bangalore, Hyderabad, Pune & Ahmedabad

Job Description:

We are seeking an exceptional Fullchip STA Lead to take a key role in our semiconductor design team. As Fullchip, STA lead you will get opportunity to work with talented and passionate STA engineers and create designs that push the envelope on performance, energy efficiency and scalability. you will lead the STA for cutting-edge high speed and complex large ASIC. You will collaborate closely with cross-functional teams to ensure the successful delivery of high-quality designs.

Responsibilities:

• Responsible for leading a team of STA engineers and close high frequency, lower tech node complex designs.
• Full chip timing analysis from early investigation to final implementation and tape out.
• Propose or develop timing methodologies to support the timing flow from RTL synthesis to implementation and timing closure.
• Work with architects and logic designers to generate block and full chip timing constraints.
• Analyse scenarios and margin strategies with Synthesis & Design team.
• Partner with physical design teams to close and sign off the designs through PnR and ECO cycles.
• Work with physical design team to improve interface and clock latency.
• Work on SDC for block, partition, fullchip such as define constraints, IO budgeting, merging constraints.
• Work with third party IP, derive timing signoff requirements.

Requirements:

• Bachelor's or Master's degree in Electrical Engineering or Electronics & Communications.
• Hands-on experience in ASIC timing constraints generation and timing closure.
• Expertise and advanced knowledge of industry standard timing EDA tools (Prime Time, StarRC, Tempus, Tweaker etc.).
• Deep understanding and experience in timing closure of various functional and test modes
• Expertise in deep-sub micron processes (Crosstalk delay, noise glitch, AOCV/SOCV/POCV, STA).
• Proficiency in industry-standard EDA tools from Cadence, Synopsys and Mentor Graphics for Synthesis, PnR, Signoff Closure.
• Strong scripting skills using TCL, Python, or Perl for design automation and tool customization.
• Excellent problem-solving and analytical skills, with a track record of delivering high-quality designs on schedule.
• Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment.
• Problem solver, Efficient written and verbal communication, Excellent organization skills and Mentorship quality.
• Ability to work cross-functionally with various teams and be productive under aggressive schedules.
• Proven ability to lead and mentor junior engineers, fostering their professional growth and development.

Preferred qualifications:

• Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology.
• Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for STA integration.
• Detailed Knowledge on Clocking methodology and various techniques to improve skew, latency, timing, power.
• Familiarity with low-power design techniques and methodologies, such as multi-voltage domains and power gating using UPF.
• Expertise in Timing Closure including setup, hold, DRV, SI, Interface issues.

Contact

Uday

muday_bhaskar@yahoo.com

Mulya Technologies

"Mining the Knowledge Community"