Lead DFT Engineer
NXP Semiconductors
5 - 10 years
Noida
Posted: 11/07/2026
Job Description
Digital Design Engineer with hand on experience in Scan insertion, ATPG, GLS. He/She will be responsible for understanding the DFT architecture of the design and providing the scan insertion collaterals to the implementation team, to enable scan insertion flows during synthesis. Should have proficiency in industry-standard DFT tools such as Mentor Tessent, Synopsys DFT Compiler, Cadence Encounter Test. Should be able to contribute to ATPG at partition and SoC level. . Should have experience with DFT GLS simulation tools and methodologies, including fault modeling and coverage analysis. Should be familiar with industry standards such as IEEE 1149.1 (JTAG) and IEEE 1687 (IJTAG). Effective communication and teamwork skills, with the ability to collaborate across functions.
#LI-2734About Company
NXP Semiconductors is a global leader in semiconductor manufacturing, headquartered in Eindhoven, Netherlands. The company specializes in developing secure, connected solutions for embedded systems, powering applications in automotive, industrial, mobile, and IoT markets. NXP is particularly known for its innovations in automotive electronics, including advanced driver-assistance systems (ADAS), secure vehicle access, and in-vehicle networking. Its portfolio also includes microcontrollers, sensors, and wireless connectivity products. With a focus on enabling smarter, safer, and more sustainable technologies, NXP is a trusted partner in advancing the future of connected devices.
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