Job Details:

Job Description:

About the Role

Intel is seeking a New College Graduate Design Verification Engineer for the Silicon Chassis team. In this role, you will contribute to the verification of next-generation interconnect and chassis IPs that underpin Intel's most ambitious SoC and platform products.

You will work alongside senior engineers to build testbenches, write constrained-random tests, close functional coverage, and root-cause simulation failures — developing end-to-end verification skills from day one.

We look for engineers who think algorithmically, write clean code, and are excited to apply the latest AI-assisted development tools as a core part of how they work. You do not need to know everything on day one; you do need strong fundamentals, genuine curiosity, and the drive to ramp fast.

Key Responsibilities

Develop testbench components, constrained-random stimulus, and functional checkers for interconnect and chassis IP under guidance of senior engineers
Write, run, and debug simulation tests; analyze failures and root-cause issues to closure with clear technical write-ups
Contribute to functional coverage plans, coverage closure analysis, and regression triage
Participate in spec reviews, design discussions, and bug triage; learn to contribute across architecture, design, and software boundaries
Use AI-assisted coding and debugging tools as an everyday part of development workflow; actively contribute to the team's productivity through automation and scripting
Continuously build depth in hardware design, verification methodology, and the chip development flow

What You Should Bring to the Team

To thrive in this role, you should demonstrate the following professional traits:

Intellectual curiosity — a genuine drive to learn new technologies, methodologies, and tools quickly
Algorithmic thinking — the ability to approach complex problems with structured, logical reasoning
Attention to detail — precision in writing tests, analyzing failures, and producing clear technical documentation
Collaborative mindset — comfort working alongside senior engineers and contributing across team boundaries
Self-motivation — the initiative to ramp fast, take ownership of tasks, and continuously build technical depth
Adaptability — openness to integrating AI-assisted tools and modern workflows as a core part of daily work

Qualifications:

This position is not eligible for Intel immigration sponsorship.

This is an entry-level position. Skills and experience may be obtained through coursework, projects, internships, or work experience.

Minimum Qualifications

BS or MS in Electrical Engineering, Computer Engineering, or Computer Science
Strong foundation in logic design and digital circuits; ability to read and reason about RTL is essential
Strong algorithmic thinking and software fundamentals; demonstrated proficiency in at least one of C/C++, Python, or SystemVerilog through coursework, projects, or internships
Coursework or project exposure to two or more of the following: computer architecture, parallel and distributed computing, operating systems, hardware/software interfaces, or VLSI design
Demonstrated use of AI coding assistants as a regular part of coursework or project work — not occasional use, but as a genuine productivity tool
Internship or research experience in a hardware design or verification environment

Preferred Qualifications

Coursework or project work in hardware verification, FPGA design, or RTL simulation (ModelSim, VCS, Questa, or similar)
Exposure to SystemVerilog, UVM concepts, or assertion-based verification through coursework, self-study, or internship
Familiarity with standard bus protocols (AXI, AHB, PCIe) or cache/memory hierarchy concepts
Comfort working in Linux environments, using version control (git), and writing build/test automation scripts
Demonstrated project work (senior design, research, hackathon, or personal) involving hardware modeling, algorithm implementation in HDL, or hardware-software co-design

Intel is an equal opportunity employer committed to diversity and inclusion in the workplace.

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, California, Santa Clara

Additional Locations:

Business group:

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $105,650.00-149,150.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Design Verification Engineer

intel

Job Description