Physical Design - Engineer

General Summary:

• Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization.
• Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions.
• Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts
• Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes
• Good understanding of clocking architecture.
• Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc.
• Well versed with Tcl/Perl Scripting
• Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers.
• Strong problem-solving skills and good communication skills.

Minimum Qualifications:

• • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.Experience level: BE + 1-2 years / ME with internship experience in VLSI