Job description:

Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.

· The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed design. The responsibility includes participating in or leading next generation PHY IP physical design, methodology and flow development.

· Working closely with RTL design team & Analog Team to ensure successful tapeouts.

· Responsibility includes participating in or leading next-generation physical design, methodology, and flow development in advanced technology nodes

Position Requirements:



· B.Tech/BE/ME/Mtech with hands-on experience in physical design and verification.

· Experienced with ASIC design flow, hierarchical physical design strategies, and methodologies and understanding deep sub-micron technology issues.

· Solid knowledge of LP Design, DFT, static timing analysis, EM/IR-Drop/crosstalk analysis, formal verification, physical verification, and DFM.

· Successful track records of taping out complex IPs & SoCs at 16/10/7/5 nm Power user of Cadence implementation tools, such as Genus, Innovus, Quantus, Tempus, PVS, Voltus.

· Automation and programming-minded, coding experience in Makefile/Tcl/Tk/Perl.