Sr Principal Application Engineer
Cadence Design Systems, Inc.
8 - 10 years
Bangalore
Posted: 8/10/2023
Job Description
Requirements:
• B.Tech./M.Tech. or equivalent in Electrical, Electronics or Computer Engineering.
• At least 8+ years of direct experience in formal verification.
• Ability to identify the suitable design for FV and analyze its complexity.
• Experience of creating formal test plan and test bench containing list of required checkers.
• Ability to dive deep in the RTL structures to understand the design and debug problems.
• Experience with CDC, LP , Security formal is a plus.
• Experience of at least one industry-wide used formal tools such as JG, VC Formal or Questa Formal.
• Proficient in SV and SVA.
• Perl/python/TCL scripting is a plus.
About Company
Cadence Design Systems, Inc., headquartered in San Jose, California, is an American multinational computational software company, founded in 1988 by the merger of SDA Systems and ECAD, Inc. The company produces software, hardware, and silicon structures for designing integrated circuits, systems on chips (SoCs), and printed circuit boards. Cadence Design Systems began as an electronic design automation (EDA) company, formed by the 1988 merger of Solomon Design Automation (SDA), co-founded in 1983 by Richard Newton, Alberto Sangiovanni-Vincentelli, and James Solomon, and ECAD, a public company co-founded by Ping Chao, Glen Antle, and Paul Huang in 1982. SDA's CEO Joseph Costello was appointed as CEO of the newly combined company.
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