Position Description:

• Functional Verification Engineer for DDR Memory Controller and PHY IP development team.
• The role would include functional verification of the DDR Memory Controller and PHY IP solution of Cadence.
• The work involved will be working with the existing functional verification environment, the addition of new features into the verification environment, ensuring various customer configurations are clean as part of verification regressions, supporting customers in case of any issues with using the verification environment, and functional and code coverage.
• The engineer would be responsible to ensure that the design is in line with the technical and quality requirements set for the team – particularly with respect to functional and code coverage.

Position Requirements:     

    

• BE/BTech/ME/MTech - Electrical / Electronics / VLSI with experience as a design and verification engineer, with a large portion of the recent work experience on verification environment development.
• Strong background in functional verification fundamentals, environment planning, test plan generation, environment development is a must.
• System Verilog experience and experience with UVM based functional verification environment development are required.
• Prior RTL Design experience using Verilog is a must – so that the verification engineer is self-sufficient for most aspects of debugging.
• The Latest DDR Protocol experience is highly desirable. Prior experience in functional verification and debugging of complex protocols is a must.
• AXI3/4 experience is desirable.
• Prior experience in IP development teams would be an added advantage.