Design Engineering Architect
Cadence Design Systems, Inc.
3 - 5 years
Bangalore
Posted: 30/10/2023
Job Description
Job Description:
1. Proficient in Verilog coding and RTL design, data path designs,
2. Knowledge of RTL checks ex- LINT, SDC, CDC
3. Familiar with synthesis flow and timing constraints
4. Experience in writing Verilog testbench and running simulations.
5. Desired Protocols knowledge – USB, PCIe, MIPI(DPHY), HDMI/Display
Nature of work:
The Candidate will be responsible for the design and implementation of high-speed SerDes PHY at the cutting edge nodes.
Responsibilities include the architecture of high-speed SerDes IP, design, lint, synthesis, static timing analysis, DFT, formal verification, at block, core, and chip levels.
Work closely with Analog design teams to co-develop algorithms, feedback design loops as well as high speed critical digital circuits
Requirement:
the Candidate is expected to have a good understanding of the digital design flow.
Proficient in Verilog coding
Proficient in high-speed design, RTL coding, datapath designs, working at GHz frequencies.
About Company
Cadence Design Systems, Inc., headquartered in San Jose, California, is an American multinational computational software company, founded in 1988 by the merger of SDA Systems and ECAD, Inc. The company produces software, hardware, and silicon structures for designing integrated circuits, systems on chips (SoCs), and printed circuit boards. Cadence Design Systems began as an electronic design automation (EDA) company, formed by the 1988 merger of Solomon Design Automation (SDA), co-founded in 1983 by Richard Newton, Alberto Sangiovanni-Vincentelli, and James Solomon, and ECAD, a public company co-founded by Ping Chao, Glen Antle, and Paul Huang in 1982. SDA's CEO Joseph Costello was appointed as CEO of the newly combined company. Following the resignation of Cadence's original CEO Joe Costello in 1997, Jack Harding was appointed CEO. Ray Bingham was named CEO in 1999. In 2004, Mike Fister became Cadence's new CEO.
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