VLSI - DFT Staff Engineer/Principal Engineer

Company: Eteros Technologies India Private Limited

Eteros Technologies, Inc. is a Semiconductor Engineering services startup, head quartered in the heart of the Silicon Valley, San Jose, CA, USA. Eteros Technologies India Pvt Ltd is a wholly owned subsidiary offices in Bangalore, Hyderabad and Ahmedabad.

Our engineers work on cutting edge technology nodes while working on the state-of-the art designs in the AI/ML, Datacenter, Automotive and 5G domains.

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We are looking for a DFT Lead/Principal Engineer with strong expertise in DFT implementation for complex SoCs. This is a hands-on leadership role where you will own DFT architecture, methodologies, and execution for advanced technology nodes.

Location: Bangalore/Hyderabad/Ahmedabad

Experience Level: 10+ Years

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Summary

• Minimum 10yrs+ experience in DFT implementation
• Must have worked on Scan Insertion, MBiST, ATPG, Simulations
• Must have experience with Synopsys DFT tools & Flows
• Experience in DFT timing closure preferred
• Experience in multi-die HBM/Memory testing with Synopsys tools preferred
• Work hands-on on critical tasks of DFT implementation
• Own the DFT implementation flows, methodologies and execution of SoCs Experience
• Experience in all phases of the DFT pre and post-Si for large SoCs
• Implement DFT of SoC/Full-chip-level and/or high-speed cores/blocks
• Experience in high-speed, low-power, mixed-signal SoCs is a plus
• Preferably worked on 5nm/7nm/12nm/14nm/16nm nodes at the major foundries
• Experience in developing DFT architecture, Test-plan, implementation methodologies
• Experience in scan insertion, memory-BIST, JTAG/IJTAG, CTL, IEEE 1149.1/1500 wrappers, BSCAN, Compression, ATPG, Simulations, post-Si testing/debug
• Experience in manual test-point insertion, improve coverage targets, high-compression
• Experience in hierarchical ATPG, OCC/OPCG, power-aware scan/ATPG methodologies
• Experience in test-mode constraints generation and test-mode timing closure
• Experience in patter generation for foundry, post-Si support/debug
• Thorough understanding of digital design, timing analysis, and physical design process
• EDA Tools: Cadence (Encounter-Test, Modus-DFT, Tempus, Conformal), Mentor (Tessent tool suite), Synopsys (DFTC, Tetramax, TestMax-DFT, SMS, PTSI)

Requirements

BTech/MTech/PhD with in Electrical or Computer engineering

10-17years of hands-on experience with DFT and test flow with commercial EDA tools for large and complex SOCs

Strong fundamental knowledge of DFT techniques include JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IEEE 1500 Std. and MBIST

Experience with Cadence & Synopsys DFT tools is required.

Strong programming skills in Perl/TCL/C++ and shell scripting is required

Must be able to solve complex problems and independently drive tasks to completion in a timely manner.

Be able to work under limited supervision and take complete accountability.

Excellent written and verbal communication skills

What's in it for you

Work on leading edge technologies

An opportunity for career development and growth

Competitive compensation

Medical Benefits and more