Verification Lead

Job Description (Brief):

• Verify PCIe Gen5 / Gen6 / Gen7 IP/subsystem using SystemVerilog & UVM
• Strong understanding of PCIe protocol , LTSSM, TLP/DLLP, PIPE, link training & equalization
• Experience with high-speed protocols , error handling, power management, and compliance
• Develop and maintain UVM testbenches , sequences, scoreboards, and assertions
• Debug complex protocol-level issues using waveform analysis
• Collaborate with design, architecture, and validation teams
• Exposure to VIPs, coverage closure, regressions , and performance verification

Must-Have Skills:

• PCIe Gen5/Gen6 (Gen7 exposure is a plus)
• SystemVerilog, UVM
• Protocol verification & debugging
• Strong hands-on in coverage, assertions, and regressions

Good to Have:

• PCIe compliance testing experience
• Scripting (Python / Perl / TCL)
• Experience with multi-lane, low-power, and high-bandwidth designs

Location- Bangalore/Noida

Notice period- 0-60 days

Experience - 5- 15 years