Verification Engineer
ScaleFlux
2 - 5 years
Bengaluru
Posted: 26/02/2026
Job Description
Verification Engineer
At ScaleFlux, we are a family unit powered by diversity, inclusion, transparency, respect, integrity, and passionfor both our clients and our people. Our business growth depends on your professional development, as we collaborate, share ideas and innovations, and invest in our future. By forging meaningful partnerships with our people, we come together with a shared purpose, exceeding our goals. This keeps us nimble, ahead of the competition, and at the forefront of our industry. Our continued success begins with you.
ScaleFlux helps customers harness data growth as a competitive advantage by building products that reduce complexity and accelerate the creation of value from data. In our first phase of rethinking the data pipeline for the modern data center, ScaleFlux built a better SSD by embedding computational storage technology into flash drives. Now, customers can gain an edge by deploying storage intelligence to optimize their data center infrastructure for workloads like databases, analytics, IoT, and 5G.
For a detailed information about us visit the company website:www.scaleflux.com
Location: Bangalore, KA. India
Minimum Qualifications
- BE/BS degree (Masters preferred) in Electrical/Electronics/VLSI Engineering with 4 to 10 years of relevant verification experience
- Expertise in CPUSS C-based verification.
- Strong fundamentals in digital ASIC design and verification
- Expertise in ARM cores and related infrastructure (like Coresight, NIC/NOC, other bus interconnects etc.)
- Familiarity with AMBA bus protocols, system memory hierarchy, system debug infrastructure and multi-core SOC
- Strong experience with Verilog, SystemVerilog, UVM and/or other
- Formal Verification experience is a plus Understanding of major SOC interfaces like PCIE, NVMe, CXL, DRAM, Flash, I2C, SSP, UART is desirable
- Understanding of IP designs and verification requirements
- Strong test creation, debug capability and functional coverage understanding
- Understanding of Gate Level Simulations (GLS) with timing and related debug capability
- Excellent communication and leadership quality to technically mentor and lead a team of verification engineers
Roles And Responsibilities
- Develop verification environment and test plans driven by functional coverage
- Develop test cases and execute them for verification of the design (both IP and SoC level)
- Run verification simulations and debug design and RTL issues
- Work closely with design team for continuous improvement of design quality through verification Review the test plans, verification tests and coverage for other team members
- Work closely with design team for continuous improvement of design quality through verification Review the test plans, verification tests and coverage for other team members
- Contribute on GLS, emulation, FPGA based and Post Si validation
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