Test Design Engineer

Role: DFT Lead

Location: Bangalore

Experience: 7+ Years

Notice Period: 030 Days

Work Mode: WFO

Key Responsibilities:

• End-to-end DFT implementation at block and top level including SCAN, MBIST, LBIST, BSCAN, and IJTAG
• Hierarchical scan insertion and complete ATPG flow, including coverage analysis and debug
• MBIST integration and RTL-level DFT verification
• LBIST coverage analysis and gate-level simulation (GLS) enablement
• IEEE 1149.1 JTAG & IJTAG architecture definition and implementation
• DFT verification, lint checks, and equivalence checks
• ATE pattern development, silicon bring-up support, and post-silicon debug
• Integration and test strategy understanding for Analog IPs
• Close collaboration with RTL, Physical Design, and Verification teams
• Ability to manage multiple designs and deliver high-quality results

Qualifications:

• B.E./B.Tech/M.E./M.Tech in ECE, EE, VLSI, Computer Engineering, or related disciplines
• 6+ years of hands-on experience in DFT
• Strong fundamentals in SCAN, MBIST, LBIST, BSCAN, IJTAG, and IP test modes
• Proficiency with EDA tools such as Tessent, Genus, Fusion Compiler, VCS, Conformal/Formality, SpyGlass
• Strong ATPG coverage analysis, DFT debug, and verification experience
• Proficient scripting skills in Perl, TCL, and/or Python
• Excellent communication, leadership, and cross-functional collaboration skills