Synthesis Engineer

Job Title: Synthesis Engineer

Experience: 5+ Years

Location: Bengluru

Employment Type: Full-time

Job Summary

We are seeking a skilled Synthesis Engineer to join our VLSI Design team. The candidate will be responsible for RTL-to-Gate synthesis, timing optimization, and supporting the physical design team for timing closure in advanced semiconductor technologies.

Key Responsibilities

• Perform RTL to Gate-Level synthesis using industry-standard tools.
• Optimize designs for timing, area, and power.
• Create and maintain timing constraints (SDC).
• Work closely with RTL, STA, and Physical Design teams for design optimization and timing closure.
• Analyze and resolve setup/hold violations during synthesis stages.
• Support logic equivalence checking (LEC) between RTL and synthesized netlist.
• Participate in design implementation and debugging.

Required Skills

• Strong understanding of digital design and synthesis flow.
• Experience with Synopsys Design Compiler / Fusion Compiler / Cadence Genus.
• Knowledge of timing constraints, STA basics, and low-power design techniques.
• Familiarity with RTL coding (Verilog / SystemVerilog).
• Good understanding of ASIC design flow.
• Experience with TCL scripting is preferred.

Education

• Bachelors or Masters degree in Electronics / Electrical Engineering / VLSI / Microelectronics or related field.