Static Timing Analysis Lead

Job Description

Role/Skill: Synthesis , Constraints & STA Lead

Experience: 8+ yrs

Location: Bangalore

Key Responsibilities:

• Should have strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools.
• Experience with writing timing constraints for synthesis, STA, timing closure, and pipelining at different levels for performance optimization and timing closure.
• Experience in all aspects of timing closure for multi-clock domain designs.
• Should be familiar with MCMM synthesis and optimization.
• Should have good understanding of low-power design implementation using UPF.
• Experience with scripting language such as Perl/ Python, TCL.
• Experience with different power optimization flows or technique such as clock gating.
• Should be able to work independently with design, DFT and PD team for netlist delivery, timing constraints validation.
• Should be able to handle ECOs and formal verification and maintain high quality matrix. Should have deep Knowledge in Formal Verification(LEC) and Debugging Non-equivalence checks

Required Skills:

• Strong hands-on experience with EDA tools like Cadence Innovus, Synopsys ICC2, or Mentor Olympus.
• Deep understanding of physical design flow, Primetime.
• Experience in hierarchical design, multi-voltage domains, and timing closure.
• Proficiency in scripting (Tcl, Perl, Python) for automation and debugging.