Staff Digital Design Engineer (RTL)

We are seeking a Staff Digital Design Engineer to join one of our premier client Memory Interface Devices (MID) Business Unit. In this high-impact role, you will lead the micro-architecture and design of high-performance chips that power AI, HPC, datacenters, and cloud applications.

You will collaborate with expert cross-functional teams to deliver robust, power-efficient, and high-throughput solutions using cutting-edge DDR and LPDDR technologies.

Location: [Bangalore / Hybrid]

Experience: 5+ Years

Key Responsibilities

• Lead Design: Drive RTL design and micro-architecture development for memory interface digital blocks and subsystems.
• End-to-End Ownership: Own the full design flow from specification and RTL coding to working with PnR teams on timing closure and release.
• Cross-Functional Collaboration: Partner with analog/mixed-signal teams for PHY/controller co-design and verification teams to define coverage goals and corner-case scenarios.
• Technical Quality: Drive design reviews, documentation, and best practices across the BU.
• Project Support: Support silicon bring-up, debug, characterization, and post-silicon validation.
• Mentorship: Mentor junior engineers and influence engineering best practices across the organization.

Required Qualifications

• Education: BE/BTech in Electrical/Electronics Engineering or a related field (ME/MTech preferred).
• Experience: 5+ years in digital design/RTL development for SoC, IP, or complex subsystems.
• Technical Expertise: * Memory Standards: Deep knowledge of DDR (2/3/4/5), LPDDR (2/3/4/5/5X), and MRDIMM/RDIMM.
• Languages: Strong hands-on expertise in SystemVerilog or Verilog.
• Tooling: Proficiency in synthesis, STA, CDC/RDC methodologies, and linting tools.
• Digital Concepts: Solid understanding of high-speed design, clocking, resets, and power domains.

If you are open to exploring this opportunity, please apply and share your resume to Heena (linkedin.com/in/heena-kausar-3a2b94a4) at heena.k@randstad.in