Staff DFT Engineer

Job Description

We are seeking a Staff DFT Engineer to own and drive the complete DFT strategy for complex SoCs from architecture through production silicon. The role requires deep hands-on expertise, strong technical judgment, and the ability to lead and mentor engineers while collaborating closely with design, PD, validation, and manufacturing teams.

The ideal candidate operates independently, makes architecture-level decisions, and is accountable for test quality, coverage, and silicon readiness.

Responsibilities

• Define chip/subsystem DFT architecture: scan, compression, LBIST, MBIST, boundary scan, test access
• Drive early RTL testability and balance coverage, test time, power, area, schedule trade-offs
• Lead scan insertion, stitching, DFT DRC closure
• Execute ATPG (stuck-at, transition, path delay), compression, pattern optimization
• Own DFT signoff (coverage, IR drop, power, timing impacts)
• Debug DFT issues across RTL, synthesis, P&R, and gate-level
• Generate/analyze ATPG patterns; sign off fault coverage, pattern volume, test time
• Diagnose coverage gaps and drive methodology fixes
• Support silicon bring-up, failure analysis, yield ramp
• Debug scan/BIST/tester failures; drive DFT ECOs
• Collaborate with ATE/manufacturing to improve yield and robustness
• Act as DFT technical lead; mentor engineers; define best practices

Qualification

• 5+ years hands-on DFT experience; led end-to-end SoC execution and developed DFT architecture from scratch
• Strong expertise in LBIST, ATPG, DFT DRC, scan compression/stitching, low-power DFT constraints, MBIST (with repair), Boundary Scan (IEEE 1149.1), Analog DFT, JTAG/TAP, and DFT-specific STA constraints
• Proficient with Cadence/Siemens DFT tools
• Strong Tcl/Perl/Python scripting skills
• Solid understanding of RTL design, Lint/CDC, low-power checks, and full ASIC flow

Soft Skills

• Ability to independently drive coverage closure and DFT signoff for complex SoCs
• Structured debugging approach across RTL, ATPG, scan/BIST, and silicon failures
• Clear communication of coverage metrics, risks, and silicon readiness status
• Capability to mentor engineers and lead technical design reviews
• Strong ownership mindset and execution discipline
• Ability to manage multiple deliverables under tight timelines