STA Engineers

Were Hiring | Senior STA Engineer (4-12 Years) Bangalore

Location: Bangalore

Experience: 4-12 Years

Notice Period: Immediate to 45 days

Job Description:

We are looking for an experienced Static Timing Analysis (STA) Engineer with strong expertise in constraint generation to join our VLSI team.

Key Responsibilities:

• Perform full-chip and block-level Static Timing Analysis
• Develop and validate SDC constraints (clocks, I/O, exceptions, CDC paths, etc.)
• Work closely with RTL, synthesis, PnR, and sign-off teams
• Analyze and resolve timing violations (setup/hold, recovery/removal)
• Support timing closure across multiple design stages
• Review and debug constraint-related issues

Required Skills & Experience:

• 5+ years of hands-on experience in STA
• Strong expertise in constraint generation and validation
• Experience with industry tools such as PrimeTime
• Solid understanding of timing concepts, clocks, and low-power designs
• Good debugging and communication skills