STA engineer
Mirafra Technologies
2 - 5 years
Noida
Posted: 28/02/2026
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Job Description
STA timing Closure SDC generation Debugging and validation
3 year+, Noida location
- Hands-on experience in ASIC timing constraints generation and timing closure
- Expertise and advanced knowledge of industry standard timing EDA tools (Tempus preferred)
- Deep understanding and experience in timing closure of various functional and test modes
- Expertise in timing convergence issues associated with deep-sub micron processes (crosstalk delay, noise glitch, POCV, IR-STA)
- Proficient in scripting languages (csh/bash, TCL and Python)
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