STA timing Closure SDC generation Debugging and validation

3 year+, Noida location

Hands-on experience in ASIC timing constraints generation and timing closure
Expertise and advanced knowledge of industry standard timing EDA tools (Tempus preferred)
Deep understanding and experience in timing closure of various functional and test modes
Expertise in timing convergence issues associated with deep-sub micron processes (crosstalk delay, noise glitch, POCV, IR-STA)
Proficient in scripting languages (csh/bash, TCL and Python)

STA engineer