STA Engineer

Job Title: STA Engineer (Static Timing Analysis)

Experience: 5+ Years

Education: B.E / B.Tech / M.Tech in Electronics, VLSI.

Location: Bangalore

Job Description:

We are looking for a skilled STA Engineer with 5+ years of experience in Static Timing Analysis and timing closure for ASIC/SoC designs. The candidate should have strong knowledge of timing analysis, signoff, and debugging timing violations.

Key Responsibilities:

• Perform Static Timing Analysis (STA) for block and full-chip designs.
• Analyze and fix setup, hold, and timing violations.
• Work closely with Physical Design and RTL teams for timing closure.
• Handle timing constraints (SDC) and timing checks.
• Support timing signoff using industry tools.
• Debug timing issues across different corners and modes.

Required Skills:

• Strong knowledge of STA concepts and timing closure.
• Hands-on experience with Synopsys PrimeTime or Cadence Tempus.
• Experience in ASIC/SoC design flow.
• Understanding of timing constraints (SDC), ECO, and signoff flows.
• Experience with advanced nodes (28nm / 16nm / 7nm / 5nm) is a plus.