SoC RTL Design - Memory Team

Position Summary

Role and Responsibilities

• Experience in leading the team technically

• Experience in Architecture, Micro-Architecture, Designing and RTL coding using Verilog /System Verilog/VHDL

• Working experience in complex IP Design in the High speed serial protocols like UFS, PCIe, SAS, NVMe, Fabrics

• Design QC using lint/CDC/DFT. Compile, elaboration and simulations for QC

• Experience with VCS, NCSIM, Verdi and Spyglass

• Experience in synthesis using Synopsys Design Compiler (DC) and developing timing constraints (SDC) and Timing analysis

• Understanding of storage controller Architectures, Peripherals, Buses/Interconnects and Power Management

• Understanding of Bus Architectures (AXI/AHB), NOC (Network-on-Chip) and ARM CPU Architectures

Skills and Qualifications

Company Information

Samsung Semiconductors India R&D (SSIR) is one of the largest overseas R&D centers of the Semiconductors Business of Samsung Electronics. At SSIR, we are committed to building a ‘smart’ and ‘simpler’ future through all our products. Our 1000-strong team of engineers, works on advanced semiconductor technologies, contributing to reliable, high performance solutions that are part of many well-received Samsung products. Our differentiated offerings in System on Chip (SoC), Memory and Storage have contributed immensely to Samsung becoming the 2nd largest Semiconductor Company in the world. The Memory Solutions Team (MST) Controller development  is at the forefront of designing, developing, and commercializing cutting edge storage controllers for SSD based on NVMe, UFS, SAS, NVMe over Fabrics and high speed peripheral bus standards like PCIe.

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