SoC Mixed Signal Verification Engineer

Key Responsibilities

• Develop and maintain mixed-signal verification environments for SoC designs
• Execute AMS and DMS flows using industry-standard tools
• Work closely with analog/digital design teams to understand IP/SoC requirements
• Debug and resolve issues across analog, digital, and mixed-signal domains
• Support full-chip mixed signal verification including UVM-MS environments
• Document verification plans, results, and methodologies
• Drive continuous improvement of verification strategies and test coverage

Education Qualifications (Mandatory)

• M.Tech in VLSI or Microelectronics with 3+ years of relevant experience, OR
• B.Tech in Electronics (or related discipline) with 5+ years of industry experience.

Required Skills & Competencies

1. Modelling

• No prior modelling experience required.
• Must have understanding of hardware description languages: Verilog / Verilog-A / Verilog-AMS

2. Verification Methodology

• Strong awareness and understanding of UVM methodology.

3. Analog Circuit Understanding

Must understand specifications of major analog IPs including:

• Data Converters: ADC / DAC
• Power Management Units (PMU)
• Clocking Blocks: PLLs, Watchdog Timers, Crystal Oscillators
• High-Speed Interfaces: MPHY, SerDes, Ethernet, USB
• MIPI D-PHY

Additional required analog skills:

• Understanding Transient & DC simulations
• Knowledge of AC & Stability Analysis is an added advantage

4. Tools Knowledge

Hands-on experience with the following tools is required:

• Operating Systems - Unix / Linux basics
• Simulation Tools (Cadence) - Xcelium, Spectre / SpectreX / SpectreFX
• Simulation Tools (Synopsys) - XA, VCS

5. Verification Flows

Candidates must have strong understanding and experience with:

• DMS (Digital-on-Top) & AMS (Analog-on-Top) flows at full-chip/ASIC/SoC level
• ADE Explorer / ADE Maestro GUI-based DMS/AMS flows
• UVM-MS methodology
• Power-aware Mixed Signal Verification (added advantage)
• Spice-based Full-chip Power Leakage Analysis (PLA):Hierarchical sub-circuit power
• Floating gates
• DC leakage path analysis
• GLS (Gate Level Simulation) import and GLS-based MS verification (added advantage)

6. Ownership & Behavioral Expectations

• Ability to independently create testcases and testbench implementations (Must)
• Strong scheduling discipline and ability to meet timelines (Must)
• Excellent debugging skills (Must) in both analog and digital domains
• Commitment to on-time delivery with high-quality results (Must)
• Flexibility to adapt to evolving project requirements
• Proactive mindset for exploring and improving verification methodologies

Preferred Qualifications (Good to Have)

• Experience with power-aware verification
• Exposure to AMS modelling
• Understanding of high-speed interface standards and protocols
• Knowledge of advanced simulation optimization techniques