SOC Design Verification Engineer

Were Hiring SoC/Subsystem Design Verification Experts!

Do you have 410 years of experience in SystemVerilog & UVM ? Passionate about testbench creation, debugging, and coverage closure ? This role is for you!

Must-have skills:

SystemVerilog, UVM, SVA

Protocols: PCIe, UCIe, CXL, NVMe, AXI, Ethernet, DDR/LPDDR/HBM

EDA tools: Synopsys VCS, Cadence Xcelium, Verdi

Scripting: Python/Perl/Tcl

Version control: Git, Perforce

Bonus: Power-aware simulations (UPF)

If youve worked on full-chip/subsystem DV projects and love solving complex verification challenges, lets connect!

DM me or apply today!