SoC / Chip Lead & RTL design Manager

We are looking for an RTL Design Manager (Ethernet) to lead high-impact ASIC/SoC development

Location: Bangalore | Hyderabad | Remote

Experience: 10+ years

Role Title: SoC / Chip Lead RTL Manager

Minimum Qualifications:

• Strong expertise in Ethernet protocols and architecture.
• Expertise on Ethernet Subsystem Integration.
• Experience with Verilog / SystemVerilog RTL design.
• Understanding of high-speed interfaces and networking protocols.
• Experience with CDC, lint, synthesis, and timing analysis.
• Familiarity with AXI / AHB / APB bus protocols.
• Strong debugging and problem-solving skills.

If you are interested in this position, please apply to this requisition/ mail us at viswanadha.reddy@bitsilica.com