SeniorPrincipal ASIC RTL Design Engineer (SoC/Subsystem)

Proxelera is Indias premium chip and system software product engineering partner. Our engineers take extreme passion in your assignments and deliver through their years of high quality experience to make your product successful. We understand the challenges of all aspects of product engineering right from design planning stage to post silicon work. We also offer you unparalleled quality of service in productization of your chip through reference system design and system software development.

Were hiring an RTL Design Engineer who can own complex SoC or large subsystem blocks end-to-end. Youll define micro-architecture from specs, develop clean SystemVerilog/Verilog RTL, and drive integration, timing, power, and area closure with PD teams. Expect deep involvement through design reviews, bug closure, and silicon bring-up.

You should bring 8+ years of hands-on ASIC RTL experience with multiple production tapeouts, strong micro-architecture skills, AMBA protocols, low-power design, and clock/reset expertise. Solid exposure to DFT, synthesis constraints, ECO flows, and cross-team collaboration is essential.

Bonus: experience with coherency, memory subsystems, DDR/PCIe, security blocks, SVA, or performance/power analysis. FPGA-only, lint/CDC-only, or management-only backgrounds wont meet the bar.