Senior/Principal ASIC RTL Design Engineer (SOC/Subsystem)

Job Summary:

Own complete RTL design for complex SoC or major subsystem blocksfrom microarchitecture to tapeout and silicon bringup.

Responsibilities:

• Define microarchitecture and develop highquality synthesizable SystemVerilog/Verilog RTL.
• Lead design bringup, integration, and close timing/power/area with synthesis and PnR teams.
• Run design reviews, fix bugs, and support silicon validation and postsilicon debug.
• Work with DV on test plans, assertions, and coverage; support emulation/FPGA only as secondary.

MustHave:

• 8+ years handson ASIC RTL design (FPGA not counted).
• Multiple production ASIC tapeouts owning major SoC/subsystem functions.
• Strong RTL/microarchitecture skills, lowpower design, AMBA protocols.
• Experience with synthesis constraints, DFT, timing closure, ECOs.
• Proven silicon bringup for owned blocks.

Nice to Have:

• Experience with coherency, memory/IO subsystems, crypto/security.
• SVA, performance/power analysis.
• Tcl/Python scripting for design productivity.

Not Counted:

• FPGA-only experience, lint/CDC-only roles, integration without significant RTL creation, or nonhandson management/architecture roles.