Senior STA engineer

Were Hiring: STA Engineer | ACL Digital

Locations: Bangalore & Hyderabad

Experience: 4 10 Years

ACL Digital is looking for a STA Engineer with strong experience across block and/or full-chip level timing analysis to join our growing VLSI team.

Key Requirements:

• Hands-on experience in Block-level and/or Full-chip STA
• Strong expertise in Constraint Development
• Experience with Pre-layout and Post-layout STA
• Good understanding of Test Modes (Scan, Functional, etc.)
• Ability to analyze and close timing across multiple corners and modes

What Were Looking For:

• Solid debugging and timing closure skills
• Experience working in complex SoC environments
• 410 years of relevant industry experience

Interested candidates can share their resume at:

vaishnavi.suvarna@acldigital.com

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