Senior Simulation Engineer / Manager – Semiconductor Process Modeling

About The Business

Tata Electronics Private Limited (TEPL) is a greenfield venture of the Tata Group with expertise in manufacturing precision components. TEPL is building Indias first AI-enabled, state-of-the-art semiconductor foundry to serve fast-growing markets such as automotive, wireless communications, and AI with products like power management ICs, display drivers, microcontrollers (MCUs), and HPC logic.

Responsibilities

Lead development of multi-physics simulation models for semiconductor equipment processes including Etch, PVD, and CVD.

Integrate AI/ML models to accelerate simulation runtimes and enable data-driven parameter optimization.

Simulate plasma-based reactions and validate results against experimental or fab data.

Work closely with fab, equipment, and process engineering teams to align simulations with real-world process objectives.

Mentor and guide junior simulation engineers; review modeling approaches and provide technical direction.

Document simulation methodologies and deliver insights to cross-functional teams.

Contribute to long-term technology roadmaps and tool design strategies based on modeling insights.

Essential Attributes

Deep knowledge of plasma physics and reaction modeling.

Strong hands-on experience with tools like COMSOL, Ansys, or Star-CCM+.

Experience applying AI to engineering problems, including surrogate modeling and ML-based optimization.

Proactive, collaborative, and capable of influencing technical decisions across teams.

Able to balance technical depth with execution agility in a fast-paced R&D environment.

Qualifications

Masters or PhD in Chemical Engineering, Physics, Materials Science, or related fields.

8+ years of experience in semiconductor simulation, including 2+ years in a technical leadership or mentorship role.

Strong programming/scripting experience (Python, MATLAB, etc.) for simulation post-processing and AI integration.

Prior semiconductor industry experience preferred.