Senior Principal Physical Design Engineer

Job Summary

As a Senior Principal PD Engineer at NXP India, you will be a technical leader responsible for the physical design implementation of complex, high-performance integrated circuits, from RTL to GDSII. You will drive advanced methodologies, mentor junior engineers, and contribute significantly to the successful tape-out of cutting-edge SoC designs.

Job Responsibilities

* Lead and execute the full physical design flow for complex digital blocks and top-level SoCs, including floorplanning, power planning, synthesis, place and route, clock tree synthesis, static timing analysis (STA), formal verification, and physical verification (DRC/LVS).
* Develop, optimize, and implement advanced physical design methodologies and flows to achieve aggressive performance, power, and area (PPA) targets.
* Perform critical path analysis, identify timing bottlenecks, and implement effective solutions to meet timing closure on challenging designs operating at high frequencies.
* Work closely with front-end design, architectural, and DFT teams to ensure design intent is preserved and to proactively resolve integration issues.
* Drive power integrity (IR/EM) analysis and solutions, ensuring robust power delivery networks.
* Conduct comprehensive physical verification checks (DRC, LVS, DFM) and resolve all issues efficiently.
* Evaluate and recommend new EDA tools, technologies, and methodologies to enhance productivity and design quality.
* Mentor and guide junior and mid-level physical design engineers, providing technical leadership and fostering a collaborative team environment.
* Generate detailed technical documentation, reports, and presentations for design reviews and project milestones.
* Contribute to the continuous improvement of design processes and best practices within the physical design team.


Job Qualifications

* Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, VLSI Design, or a related field.
*  Bachelor's degree with 16+ years of professional experience or Master's degree with 14+ years of professional experience.

*Working knowledge on advance tech nodes 16ff and below is highly desirable.
* Expert-level proficiency with industry-standard EDA tools from Synopsys (Fusion Compiler, ICC2, Primetime, Design Compiler), Cadence (Innovus, Tempus, Genus), or Siemens (APR, Calibre).
* Deep understanding and practical experience with all aspects of the physical design flow, including floorplanning, power planning, block integration, P&R, CTS, STA, Formal Verification, and Physical Verification.
* Strong expertise in timing closure, including hierarchical STA, AOCV/POCV, multi-corner/multi-mode analysis, and complex timing constraint debug.
* Proven experience in power integrity analysis (IR/EM) and optimization techniques.
* Solid understanding of signal integrity (SI) issues and solutions.
* Proficiency in scripting languages such as Tcl, Python, and Perl for automation and flow development.
* Familiarity with low-power design techniques (UPF/CPF, clock gating, power gating, multi-Vt).
* Excellent problem-solving, analytical, and debugging skills.
* Strong communication and interpersonal skills, with the ability to effectively collaborate with cross-functional teams and mentor junior engineers.
* Prior experience in a technical leadership role, driving projects and influencing technical direction.

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