Senior Principal Firmware Engineer – Memory Technologies
Mulya Technologies
5 - 10 years
Hyderabad
Posted: 07/03/2026
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Job Description
Senior Principal Firmware Engineer Memory Technologies
Hyderabad
Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore
Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market
Senior Principal Firmware Engineer Memory Technologies
Experience
- M.Tech (1020 years) or B.Tech (1220 years) in ECE / Embedded Systems
- Strong background in baremetal firmware and memory subsystem development
Key Requirements
- Extensive firmware development experience for Memory Controllers supporting DDR4/5, LPDDR4/5/6,HBM / HBM4
- Proven experience in actual silicon bring-up (TSMC 5nm / 4nm / 3nm nodes) for DDR4/5/LPDDR5/6, including training firmware.
- Strong understanding of JEDEC memory standards.
- PCIe protocol knowledge and hands-on bring-up experience.
- Strong C programming expertise for baremetal firmware.
- Cache-coherent vs non-coherent DMA handling.
- Memory attributes, ordering, and shareability domains.
- Descriptor rings and AXI DMA engines.
- Memory barriers for CPU and device coherent access.
- Cache-line alignment of C structs and compiler hints for aligned allocations.
- Bitwise programming, atomicity, and read-modify-write hazards.
- Good understanding of compiler/linker behavior and optimization impacts (-O2/-O3).
- Strong knowledge of ARM / RISC-V / x86 assembly and C inline assembly.
- Understanding of boot flows (ROM/Flash boot).
- Experience with SiFive cores (preferred).
- C programming for SerDes configuration and register programming.
- Handling link training and error correction (e.g., PCIe).
- Debugging PHY and high-speed interface issues during bring-up.
- Proficiency in Python/Perl scripting for debug and automation.
- Experience with Make/CMake, cross-compilation, and toolchain integration.
Responsibilities
- Own architecture, design, development, and verification of baremetal firmware for memory SoCs.
- Lead silicon bring-up and SoC-level validation.
- Work closely with Design and Verification teams for memory controller and PHY enablement.
- Drive root-cause analysis, debug, and validation closure.
- Support system-level performance, stability, and reliability validation.
Contact: Uday
Mulya Technologies
Email: muday_bhaskar@yahoo.com
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