Senior Principal Firmware Engineer

Cadence Bangalore is Hiring for Senior Principal Firmware Engineer

Senior Principal Firmware Engineer

This is an opportunity to join a dynamic and growing team of experienced engineers developing physical layer IPs for industry-standard high-speed serial-link protocols , as applied to Die-2_die and Chiplet Interconnects. The successful candidate will ideally be a highly motivated self-starter who is able to work independently to complete assigned tasks and can also contribute to project leadership. It is expected that the candidate will contribute during all phases of firmware development for high speed Die-2-Die , UCIe IPs from firmware architecture development to implementation, verification, testing and customer deployment.

Responsibilities

Work closely with UCIe PHY digital and mixed signal architects to figure out the details of FW functions and sequences. Contribute during firmware architecture development and implementation of the defined firmware features.

Help to build system level prototype control software to develop/validate adaptation, equalization, and control algorithms for high speed UCIe IPs.

Validate the developed firmware in Emulation based models and in Simulations.

Implement assigned FW features and work closely with verification[simulation] and validation team to ensure the functionality and robustness of the implemented features.

Support of Validation team during electrical and system characterization during post-silicon testing. Identify any FW and HW related functionality and performance issues and implement any necessary FW improvement and work around codes to address these issues.

Support Product Engineering, System Validation and Design team to debug IP issues during customer deployment of the IP and provide hot fixes.

Create and maintain comprehensive documentation related to firmware design, development, bug fixes and compliance testing.

Desired Skills

B.Tech with 14yrs or M.Tech with 12yrs in Electrical/Electronics Engineering

Solid programming knowledge in C/C++ and Python

Understanding of wireline communication principles and digital signal processing techniques are must

Strong problem solving and communication skills

Hands on Proven experience in developing for Hardware based DSP acceleration engines

Experience with silicon validation process and debug is a plus

Experience with digital verification environment and tools is a plus

Code development and debug expertise, code profiling using IDEs

if Interested please share updated profile to dsupriya@cadence.com