Senior Physical Verification Engineer

Job Title: Senior Physical Verification Engineer

Experience: 5+ Years

Location: Bengaluru

Employment Type: Full-Time

Job Description

We are seeking a Senior Physical Verification Engineer with 5+ years of hands-on experience in physical verification for advanced ASIC/SoC designs. The ideal candidate will have strong expertise in DRC, LVS, ERC, and sign-off verification, with the ability to drive clean tape-outs and collaborate across design teams.

Key Responsibilities

• Perform Physical Verification sign-off including DRC, LVS, ERC, and Antenna checks
• Debug and resolve complex PV violations across block and full-chip levels
• Work closely with Physical Design, Foundry, and CAD teams to close verification issues
• Develop and maintain PV runsets, rule decks, and verification flows
• Perform DFM and density checks to ensure manufacturability
• Analyze and support tape-out readiness and final GDS sign-off
• Automate verification flows using TCL / Python / Perl
• Provide guidance and technical mentoring to junior engineers

Required Skills & Qualifications

• 5+ years of experience in Physical Verification for ASIC/SoC designs
• Strong hands-on experience with Mentor Calibre (DRC, LVS, PERC, DFM)
• Good understanding of foundry rule decks and advanced technology nodes
• Experience with hierarchical verification and large-scale designs
• Solid knowledge of GDSII, LEF/DEF, PDK, and tech files
• Strong debugging and problem-solving skills
• Ability to work independently and drive closure

Preferred Qualifications

• Experience with advanced nodes (7nm / 5nm / 3nm)
• Knowledge of low-power verification and ESD/Latch-up checks
• Exposure to physical design or STA flows
• Experience with multi-foundry tape-outs

Education

• Bachelors or Masters degree in Electronics & Communication Engineering, Electrical Engineering, VLSI, Microelectronics, or a related field
• M.Tech / MS in VLSI or Microelectronics is a plus