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Senior Physical Design Engineer

Scaledge Technology

5 - 10 years

Bengaluru

Posted: 12/03/2026

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Job Description

Description:

Job Title: Physical Design Engineer (58 Years Experience)

Location: Bangalore/Hyderabad


Role Overview

We are seeking an experienced Physical Design Engineer with strong expertise in advanced-node IC implementation, Cadence PD flows, and SoC-level PPA optimization. The ideal candidate will drive block-level physical design execution, ensure high quality and timely delivery, and contribute to flow/automation improvements while collaborating closely across teams.

Key Responsibilities

Physical Design Implementation: Perform floor planning, partitioning, physical implementation, and timing constraint development for complex IC designs, ensuring robust STA and EM/IR closure.

Timely, High-Quality Delivery: Own block-level delivery across multiple milestones with a focus on quality, completeness, and schedule adherence.

Clock & Routing Optimization: Optimize clock tree architectures, guide routing strategies, and drive extraction quality improvements.

PnR Execution: Manage the entire place-and-route cycle, including macro/IP integration, hierarchical design, and signoff readiness.

Leadership & Planning: Provide accurate area and effort estimates, contribute to planning, and lead execution to meet project goals and timelines.

Team Collaboration: Work effectively with cross functional peers and demonstrate strong teamwork and communication skills.

Automation & Efficiency: Develop automation to improve flow robustness, efficiency, and overall PPA quality.

Required Qualifications

Experience: 58 years of hands-on physical design implementation, flow development, and Tempus-based STA analysis.

PPA Expertise: Proven ability to meet aggressive PPA targets for SoC designs, including advanced place-and-route and IP integration.

Methodology Knowledge: Strong understanding of ASIC physical design flows, best practices, and signoff methodologies.

Tools & Technologies:

Cadence PD Flow (Required): Innovus (PnR), Tempus (STA), Quantus (Extraction), Voltus (IR/EM).

Experience with signoff tools such as Calibre.

Advanced Nodes: Hands-on experience across multiple advanced technology nodes.

Digital Fundamentals: Strong grasp of digital electronics and physical design fundamentals.

Efficiency Focus: Experience improving design flow efficiency and reducing cycle time.

Soft Skills

Strong English communication skills (written and verbal).

Excellent collaboration and interpersonal skills.

Strong analytical and problem solving abilities.

High ownership, accountability, and time management.

Education

BE or MTech in Electronics Engineering, VLSI, or a related discipline

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