Summary

Work on physical implementation of state-of-the-art SOCs at cutting edge FinFET technology nodes for various customers.

This position is for a senior-level physical design engineer who will work on

Physical implementation of a complex SOC Synthesis, Floorplan, P&R, Sign-off
Work hands-on to solve critical design and execution issues related to physical design
Own the RTL-GDS2 implementation flows, methodologies and execution of SoCs

Experience:

Experience in all phases of the IC design process from RTL->GDS2
Physical implementation of SoC/Full-chip-level and/or high-speed CPU/GPU/DSP cores
Experience in high-speed, low-power, mixed-signal SoCs is a plus
Preferably worked on 5nm/7nm/12nm/14nm/16nm nodes at the major foundries
Experience in developing PNR methodology/flow to and supporting a larger PDteam
Experience in floorplanning, clocking & power network architecture and design
Experience in low-power implementation using UPF/CPF power intent flow
Experience in I/O Ring, RDL routing, bumps and other top-level design considerations
Experience in LVS/DRC/ERC, EMIR (static & dynamic), LEC and Reliability sign-off checks
Experience in STA analysis, timing closure and defining chip sign-off criterion
Thorough understanding of digital design, timing analysis, and DFT
Good understanding of foundation IP components Standard cells, SRAMs etc.
EDA Tools: Cadence (Genus, Tempus, Innovus, Voltus), Mentor (Olympus, Calibre), Synopsys (DCT, ICC2, PT-SI, Redhawk)

Qualifications:

BTech/MTech/PhD with 4-10 years experience in physical implementation
Proven track record with multiple successful final production tape-outs
Proven ability to independently deliver results in a very fast-moving startup environment, be able to work hands-on as and guide/help peers to deliver their tasks
Be able to work under limited supervision and take complete accountability.
Excellent written and verbal communication skills

What's in it for you

Senior Physical Design Engineer