Senior Manager, Mixed Signal DV

• Define and implement verification methodologies for AMS blocks (ADCs, DACs, oscillators, IO's Power management blocks , etc.).
• Oversee development of behavioural models for analog components using Verilog-A/AMS.
• Lead simulation campaigns using mixed-signal simulators (e.g., Cadence AMS Designer, Synopsys VCS AMS).
• Ensure high coverage through functional, formal, and assertion-based verification.
• Interface with project managers and technical project leads to communicate progress and resolve issues.
• Drive adoption of reusable verification IP and automation frameworks.
• Promote best practices in AMS verification and documentation.
• Conduct verification reviews and sign-offs.
• Support post-silicon validation and debug.
• Manage and mentor a team of mixed-signal verification engineers.
• Drive hiring, performance reviews, and career development.
• Foster a culture of technical excellence and innovation

• Masters or PhD in Electrical Engineering or related field.
• 10+ years of experience in mixed-signal IC verification, with 35 years in a leadership role.

+65 ()