Senior FPGA Validation Engineer
ACL Digital
5 - 10 years
Hyderabad
Posted: 18/03/2026
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Job Description
We are hiring FPGA Validation Engineers for our Hyderabad/ Bangalore location.
Key Highlights
Role: FPGA Validation Engineer
Experience: 5+ Years
Qualification: BE/BTech or ME/MTech
Location: Hyderabad/ Bangalore
Notice Period: Immediate Joiners Only
FPGA Validation | Silicon Bring-up | Protocol Debug
looking for a Strong Senior FPGA Silicon Validation Engineers
- Strong in hands on lab-based silicon validation
- Hands-on with high-speed protocols
- FPGA RTL + Verilog and C
- Experienced in board-level debug experience (Mandatory)
Interested candidates can share their resume at kalavathi.srinivas@acldigital.com
Also feel free to refer suitable candidates from your network.
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