Senior Engineer, Design Verification Engineering

About Analog Devices

Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at www.analog.com and on LinkedIn and Twitter (X).

The Engineering Enablement team provides industry-leading tools, methodologies, services and support to accelerate product development across the company. This position is part of the Systems Verification and Validation (SVV) team within the Engineering Enablement organization. SVV is building an Incubation DV Services team that’ll serve various BUs across ADI ensuring elimination of unplanned silicon iterations by boosting DV quality and embedding best practices within BUs. We’re seeking an experienced, Formal verification candidate with prior experience in developing & implementing Formal methods. Additionally, SVV is also responsible for developing, adopting, and supporting tools, methodologies, and solutions across the entire DV landscape - including Unified Metric-Driven Verification (MDV), SystemVerilog (SV)/UVM-based methods, Mixed-Signal DV, Formal Verification, Functional Safety, Security, Portable Stimulus, and Emulation/Prototyping technologies.

About the role

In this position the successful candidate will be exposed to the entire product lifecycle from concept phase, through design, verification, implementation, and release of products to customers. They will collaborate with the wider ADI technical community, which affords an opportunity to work with many business units in ADI with exposure to many technologies and products. This is a senior role with the opportunity to create real impact within the organization and build a promising career.

Job Responsibilities:

Formal Verification Planning and Execution:

Develop and execute formal verification plans for complex digital designs, including block-level and system-level components

Define verification goals, metrics, and coverage targets to ensure thorough validation of design functionality

Model Development and Property Writing:

Create formal models and assertions using industry-standard formal verification tools and techniques

Write and debug properties, constraints, and assumptions to verify design intent and identify corner-case issues

Debugging and Issue Resolution:

Analyze counterexamples and debug failures to identify root causes of design issues

Work closely with design and RTL teams to resolve issues and ensure alignment with design specifications

Tool and Methodology Expertise:

Utilize formal verification tools such as JasperGold, Questa Formal, or equivalent to perform exhaustive verification

Stay updated on the latest advancements in formal verification methodologies and tools, and drive their adoption within the team

Collaboration and Communication:

Collaborate with architects, designers, and validation engineers to understand design requirements and constraints

Documentation and Reporting:

Document formal verification strategies, methodologies, and results for future reference and audits

Generate detailed reports summarizing verification coverage, findings, and recommendations

Position Requirements:

• Bachelors/master’s degree in electrical/Electronics/VLSI with 4-6 years of experience
• Experience with Formal tools such as Cadence Jasper, Synopsys VC Formal, Siemens Questa Formal with prior implementation experience on SoCs, CPUs, GPUs or other high performance computing devices
• Proficiency in writing SystemVerilog Assertions (SVA) or Property Specification language (PSL)
• Solid understanding of digital design concepts, RTL design, hardware description languages (Verilog, SV, VHDL)
• Strong analytical and debugging skills to identify and resolve complex design issues
• Ability to analyze counterexamples and provide actionable feedback to design teams
• Excellent communications and interpersonal skills to work effectively in a collaborative team environment
• Familiarity with scripting languages (Perl, Python, TCL) for automation
• Experience in common communication protocols such as ARM AMBA, I2C, SPI, UART is preferred

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.

Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.