Senior EDA Engineer- (Cadence Virtuoso)-Semiconductor

Deep-Tech Hiring | Senior EDA Engineer (Cadence Virtuoso)

Love breaking into Cadence Virtuoso internals and automating what others do manually?

We are seeking a highly skilled EDA Engineer with strong experience in Cadence Virtuoso , OpenAccess databases , SKILL scripting , and foundry PDK/CDK integration . The role focuses on building scalable, automated design flows for an AI-driven analog design platform .

Key Responsibilities

• Develop and optimize analog/mixed-signal design flows in Cadence Virtuoso and related EDA tools.
• Build and maintain SKILL-based automation for schematic, layout, and verification tasks.
• Configure and manage CDF parameters for foundry PDK/CDK libraries.
• Develop tools using the OpenAccess (OA) API (C++ / Python / Tcl) to access and manipulate schematic, layout, and library data.
• Integrate, validate, and maintain PDKs, pCells, symbols, DRC/LVS decks, and simulation models .
• Debug PDK, OA, and schematic-layout synchronization issues.
• Create reusable scripts, workflows, and technical documentation.
• Collaborate with AI and software teams to enable next-generation EDA automation.

Required Skills & Experience

• 38 years of hands-on experience in Cadence Virtuoso analog/mixed-signal flows .
• Strong proficiency in SKILL scripting for design automation.
• Experience working with CDF and parametric device libraries.
• Hands-on experience with OpenAccess (OA) using C++, Python, or Tcl .
• Strong understanding of foundry PDK/CDK structure , including pCells, symbols, models, and rule decks .
• Experience automating schematic, layout, and library workflows .
• Knowledge of schematic-layout synchronization (LVS, SDL) .
• Strong Linux/UNIX scripting skills.
• Familiarity with version control systems used in EDA environments.
• Strong communication and ability to work in a fast-paced startup environment .

Preferred Qualifications

• Prior experience with Cadence Virtuoso toolchains or semiconductor companies.
• Exposure to Spectre, ADE, and analog verification flows .
• Understanding of semiconductor process technology and device physics .
• Exposure to AI/ML integration in EDA workflows is a plus.

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